Espressif Systems /ESP32-C6 /EXTMEM /L1_CACHE_SYNC_PRELOAD_INT_CLR

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Interpret as L1_CACHE_SYNC_PRELOAD_INT_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_ICACHE0_PLD_DONE_INT_CLR)L1_ICACHE0_PLD_DONE_INT_CLR 0 (L1_ICACHE1_PLD_DONE_INT_CLR)L1_ICACHE1_PLD_DONE_INT_CLR 0 (L1_ICACHE2_PLD_DONE_INT_CLR)L1_ICACHE2_PLD_DONE_INT_CLR 0 (L1_ICACHE3_PLD_DONE_INT_CLR)L1_ICACHE3_PLD_DONE_INT_CLR 0 (L1_CACHE_PLD_DONE_INT_CLR)L1_CACHE_PLD_DONE_INT_CLR 0 (CACHE_SYNC_DONE_INT_CLR)CACHE_SYNC_DONE_INT_CLR 0 (L1_ICACHE0_PLD_ERR_INT_CLR)L1_ICACHE0_PLD_ERR_INT_CLR 0 (L1_ICACHE1_PLD_ERR_INT_CLR)L1_ICACHE1_PLD_ERR_INT_CLR 0 (L1_ICACHE2_PLD_ERR_INT_CLR)L1_ICACHE2_PLD_ERR_INT_CLR 0 (L1_ICACHE3_PLD_ERR_INT_CLR)L1_ICACHE3_PLD_ERR_INT_CLR 0 (L1_CACHE_PLD_ERR_INT_CLR)L1_CACHE_PLD_ERR_INT_CLR 0 (CACHE_SYNC_ERR_INT_CLR)CACHE_SYNC_ERR_INT_CLR

Description

Sync Preload operation Interrupt clear register

Fields

L1_ICACHE0_PLD_DONE_INT_CLR

The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done.

L1_ICACHE1_PLD_DONE_INT_CLR

The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done.

L1_ICACHE2_PLD_DONE_INT_CLR

Reserved

L1_ICACHE3_PLD_DONE_INT_CLR

Reserved

L1_CACHE_PLD_DONE_INT_CLR

The bit is used to clear interrupt that occurs only when L1-Cache preload-operation is done.

CACHE_SYNC_DONE_INT_CLR

The bit is used to clear interrupt that occurs only when Cache sync-operation is done.

L1_ICACHE0_PLD_ERR_INT_CLR

The bit is used to clear interrupt of L1-ICache0 preload-operation error.

L1_ICACHE1_PLD_ERR_INT_CLR

The bit is used to clear interrupt of L1-ICache1 preload-operation error.

L1_ICACHE2_PLD_ERR_INT_CLR

Reserved

L1_ICACHE3_PLD_ERR_INT_CLR

Reserved

L1_CACHE_PLD_ERR_INT_CLR

The bit is used to clear interrupt of L1-Cache preload-operation error.

CACHE_SYNC_ERR_INT_CLR

The bit is used to clear interrupt of Cache sync-operation error.

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